The present invention relates generally to design automation, and relates more particularly to path selection techniques for at-speed structural test (ASST) of integrated circuit (IC) chips.
When IC chips come off the manufacturing line, the chips are tested “at-speed” to ensure that they perform correctly (and to filter out chips that do not perform correctly). In particular, a set of paths is selected, and the set of paths is then tested for each chip in order to identify the chips in which one or more of the selected paths fail timing requirements. Selection of these paths is complicated by the presence of process variations. Because of these variations, different paths can be critical in different chips. That is, a path that is critical in one chip may not be critical in another chip, and vice versa. As such, selection of the paths that have a higher probability of being critical is typically a goal.
Selected paths are provided to an automatic test pattern generation (ATPG) tool for generation of test patterns. After ATPG, some of the paths may be un-sensitizable; only those paths that are sensitizable with test patterns are actually used to test the chips. Thus, although the pre-ATPG path selection may have found a set of paths that covers the process space reasonably well, the subset of these paths that is actually sensitizable may not cover the process space as well.
FIG. 1 is a diagram comparing the coverage of a pre-ATPG set of paths and a post-ATPG subset of these paths. Pre-ATPG, three paths have been selected: a first path covering corresponding process space 100, a second path covering corresponding process space 102, and a third path covering corresponding process space 104. However, if after ATPG the first path 100 turns out to be un-sensitizable, then only the process space covered by the second and third paths 102 and 104 will be covered by testing. Alternatively, if both the first and third paths 100 and 104 are determined to be un-sensitizable after ATPG, then only the process space covered by the second path 102 will be covered by testing. In other words, the post-ATPG process space coverage is greatly reduced compared to the pre-ATPG process space coverage. Although FIG. 1 illustrates only the “single-layer coverage” case, the results for path selection guided by “multi-layer coverage” are similar.